PRODUCT SPECIFICATIONS (R) Integrated Circuits Group LH28F008SCT-L12 Flash Memory 8M (1M x8) (Model No.: LHF08CH3) Spec No.: EL104164B Issue Date: May 7, 1999 SHARP LHF08CH3 l Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. l When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein application areas. When using in Paragraph (2), even for the precautions given in Paragraph in Paragraph (3). are designed and manufactured for the following the products covered herein for the equipment listed following application areas, be sure to observe the (2). Never use the products for the equipment listed *Office electronics *Instrumentation and measuring equipment *Machine tools @Audiovisual equipment *Home appliance *Communication equipment other than for trunk lines (2) Those contemplating using the products covered herein for the following equipment which demands hiqh reliabilitv, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. &ontrol and safety devices for airplanes, trains, automobiles, transportation equipment l Mainframe computers l Traffic control systems *Gas leak detectors and automatic cutoff devices *Rescue and security equipment mother safety devices and safety equipment,etc. and other (3) Do not use the products covered herein for the following equipment which demands extremelv hiqh performance in terms of functionality, reliability, or accuracy. equipment *Communications equipment for trunk lines *Control equipment for the nuclear power industry @Medical equipment related to life support, etc. (4) Please direct all queries and comments three Paragraphs to a sales representative regarding the interpretation of the company. of the above l Aerospace l Please direct all queries regarding of the company. the products covered herein to a sales representative Paw i 1 SHARI= LHF08CH3 1 CONTENTS PAGE 1.0 INTRODUCTION 1.1 New Features.. 1.2 Product Overview 2.0 PRINCIPLES PAGE 5.0 DESIGN CONSIDERATIONS ............................. .23 ................................................... .................................................... ................................................ ........................... 3 3 3 7 5.1 Three-Line Output Control ................................ .23 5.2 RY/BY# and Block Erase, Byte Write and Lock-Bit 23 Configuration Polling.. ......................................... 5.3 Power Supply Decoupling.. ................................ 23 5.4 V,, Trace on Printed Circuit Boards.. ............... .23 5.5 v,,, v,,, RP# Transitions.. .............................. 5.6 Power-Up/Down Protection.. ............................. 5.7 Power Dissipation .............................................. 6.0 ELECTRICAL SPECIFICATIONS.. ..................... 6.1 Absolute Maximum Ratings ............................... 6.2 Operating Conditions ......................................... 6.2.1 Capacitance ................................................. .24 .24 24 .25 25 25 25 OF OPERATION.. 2.1 Data Protection ................................................... 3.0 BUS OPERATION ................................................. 3.1 Read ................................................................... 3.2 Output Disable .................................................... 3.3 Standby ............................................................... 3.4 Deep Power-Down .............................................. 3.5 Read Identifier Codes Operation.. ....................... 3.6 Write .................................................................... 4.0 COMMAND DEFINITIONS .................................... 4.1 Read Array Command.. ..................................... 4.2 Read Identifier Codes Command ...................... 4.3 Read Status Register Command.. ..................... 4.4 Clear Status Register Command.. ..................... 4.5 Block Erase Command.. .................................... 4.6 Byte Write Command ........................................ 4.7 Block Erase Suspend Command.. ..................... 4.6 Byte Write Suspend Command.. ....................... 7 a a 6 a 8 9 9 9 12 12 12 12 12 13 13 14 6.2.2 AC Input/Output Test Conditions.. ............... .26 27 6.2.3 DC Characteristics ........................................ 6.2.4 AC Characteristics - Read-Only Operations .29 6.2.5 AC Characteristics - Write Operations.. ....... .32 6.2.6 Alternative CE#-Controlled Writes.. ............. .35 6.2.7 Reset Operations ......................................... 36 6.2.6 Block Erase, Byte Write and Lock-Bit Configuration Performance ........................... 7.0 ADDITIONAL INFORMATION ............................ 39 .40 .40 ..4 1 4.9 Set Block and Master Lock-Bit Commands.. ..... 14 4.10 Clear Block Lock-Bits Command.. ................... 15 7.1 Ordering Information ......................................... 8.0 PACKAGE AND PACKING SPECIFICATIONS Rev. 1.0 SHAi?P LHF08CH3 2 LH28FOOSSCT-L12 8M-BIT (1 MB x 8) SmartVoltage Flash MEMORY n SmartVoltage Technology - 2.7V(Read-Only), 3.3V or 5V Vcc - 3.3V, 5V or 12V Vpp n High-Performance - 120ns(5V*0.5V), 170ns(2.7V-3.6V) Read Access Time 150ns(3.3V*O.3V), n Automated Byte Write and Block Erase - Command User Interface - Status Register Enhanced Automated Suspend Options - Byte Write Suspend to Read - Block Erase Suspend to Byte Write - Block Erase Suspend to Read Extended Cycling Capability - 100,000 Block Erase Cycles - 1.6 Million Block Erase Cycles/Chip Write Interface Packaging n n Operating Temperature - 0C to +7O"C I High-Density Symmetrically-Blocked Architecture - Sixteen 64K-byte Erasable Blocks Low Power Management - Deep Power-Down Mode - Automatic Power Savings Mode Decreases Ice in Static Mode Enhanced Data Protection Features - Absolute Protection with Vpp=GND - Flexible Block Locking - Block Erase/Byte Write Lockout during Power Transitions n n SRAM-Compatible n Industry-Standard - 40-Lead TSOP ETOXTM* Nonvolatile I n Flash Techno WY I W CMOS Process (P-type silicon substrate) n Not designed hardened or rated as radiation SHARP's LH28F008SCT-L12 Flash memory with SmartVoltage technology is a high-density, low-cost, nonvolatile, ?ead/write storage solution for a wide range of applications. Its symmetrically-blocked architecture, flexible voltage and extended cycling provide for highly flexible component suitable for resident flash arrays, SlMMs and memory :ards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F008SCT-L12 offers three levels of protection: absolute protection with V,, at ZND, selective hardware block locking, or flexible software block locking. These alternatives give designers Jltimate control of their code security needs. The LH28F008SCT-L12 is manufactured on SHARP's 0.38um ETOXTM process technology. It come in ndustry-standard package: the 40-lead TSOP, ideal for board constrained applications. Based on the 28F008SA architecture, the LH28F008SCT-L12 enables quick and easy upgrades for designs demanding the state-of-the-art. `ETOX is a trademark of Intel Corporation. Rev. 1.3 LHF08CH3 3 1 INTRODUCTION This contains LH28F008SCT-L12 datasheet specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4, and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. LH28F008SCT-L12 Flash also includes memory documentation application notes and design tools which are referenced in Section 7. SmartVoltage technology provides a choice of Voc and V,, combinations, as shown in Table 1, to mee system performance and power expectations. 2.7\ V,, consumes approximately one-fifth the power o 5V Vo,. But, 5V Vco provides the highest reac performance. V,, at 3.3V and 5V eliminates the neec for a separate 12V converter, while V,,=12\ maximizes block erase and byte write performance In addition to flexible erase and program voltages the dedicated V,, pin gives complete data protectior when V,+V,,,,. Table 1. Vc, and V,, Voltage Combinations Offered by SmartVoltage Technology Vpp Voltage Vr.r: Voltage 2.7V(`) -.. 3.3v, 54, l2V 3.3v 5V 5v. 12v NOTE: 1. Block erase, byte write and lock-bit configuratior operations with V,o<3.OV are not supported. Internal and VCC automatically configures read and write operations. VP, 1.1 New Features The LH28F008SCT-L12 SmartVoltage Flash memory maintains backwards-compatibility with SHARP's 28F008SA. Key enhancements over the 28F008SA include: I *SmartVoltage *Enhanced &r-System Technology Capabilities Suspend Block Locking detection Circuitb the device for optimizec Both devices share a compatible pinout, status register, and software command set. These similarities enable a clean upgrade from the 28F008SA to LH28F008SCT-L12. When upgrading, it is important to note the following differences: *Because of new feature support, the two devices have different device codes. This allows for software optimization. l VPPLK has been lowered from 6.5V to l.5V to support 3.3V and 5V block erase, byte write, and lock-bit configuration operations. The V,, voltage transitions to GND is recommended for designs that switch V,, off during read operation. technology, A Command User Interface (CUI) serves as the interface between the system processor and interna operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, byte write, and lock-bit configuration operations. A block erase operation erases one of the device's 64K-byte blocks typically within 0.3s (5V V,,, 12V VP,) independent of other blocks. Each block can be independently erased 100,000 times (1.6 million block erases per device). Block erase suspend mode allows system software to suspend block erase to read or write data from any other block. Writing memory data is performed in byte increments typically within 6u.s (5V Vcc, 12V Vpp). Byte write suspend mode enables the system to read data or execute code from any other flash memory array location. *To take advantage of SmartVoltage allow V,, connection to 3.3V or 5V. 1.2 Product Overview The LH28F008SCT-L12 is a high-performance 8M-bit SmartVoltage Flash memory organized as 1 M-byte of 3 bits. The IM-byte of data is arranged in sixteen SK-byte blocks which are individually erasable, ockable, and unlockable in-system. The memory nap is shown in Figure 3. Rev. 1.3 LHF08CH3 4 Individual block locking uses a combination of bits, sixteen block lock-bits and a master lock-bit, to lock and unlock blocks. Block lock-bits gate block erase and byte write operations, while the master lock-bit Lock-bit Jates block lock-bit modification. zonfiguration operations (Set Block Lock-Bit, Set and Clear Block Lock-Bits Master Lock-Bit, zommands) set and cleared lock-bits. The status register indicates when the WSM's block erase, byte write, or lock-bit configuration operation is iinished. The RY/BY# output gives an additional indicator of JVSM activity by providing both a hardware signal of status (versus software polling) and status masking iinterrupt masking for background block erase, for mample). Status polling using RY/BY# minimizes 30th CPU overhead and system power consumption. JVhen low, RY/BY# indicates that the WSM is 3erforming a block erase, byte write, or lock-bit zonfiguration. RY/BY#-high indicates that the WSM is ,eady for a new command, block erase is suspended :and byte write is inactive), byte write is suspended, 3r the device is in deep power-down mode. The access time is 120 ns (tAvav) over the commercial temperature range (0% to +70"(Z) ant Vc, supply voltage range of 4.5V-5.5V. At lower Vcc voltages, the access times are 150 ns (3.OV-3.6V: and 170 ns (2.7V-3.6V). The Automatic Power Savings (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). In APS mode, the typical I,,, current is 1 mA at 5V V,,. When CE# and RP# pins are at V,,, the I,, CMOS standby mode is enabled. When the RP# pin is a GND, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tpHQv) is required from RP# switching high until outputs arc valid. Likewise, the device has a wake time (t,,,,: from RP#-high until writes to the CUI are recognized With RP# at GND, the WSM is reset and the status register is cleared. The device is available in 40-lead TSOP (Thin Smal Outline Package, 1.2 mm thick). Pinout is shown ir Figure 2. Rev.1.0 SHARP LHF08CH3 5 Figure 1. Block Diagram 49 Ale A17 A16 AIS A14 An A12 NC NC WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ4 VCC CE# vcc VPP RP# 41 40-LEAD TSOP STANDARD PINOUT 1Omm x 20mm TOP VIEW GND GND DQ3 Alo As 43 A7 A6 A5 A4 DQ2 DQI DQo z A2 A3 Figure 2. TSOP 40-Lead Pinout Rev. 1.0 SHARP LHF08CH3 6 I Type 9 r r Symbol A,-Al T INPUT INPUT/ OUTPUT DQo-DQ7 CE# INPUT RP# INPUT OE# WE# INPUT INPUT RY/BY# OUTPUT SUPPLY Vcc GND NC SUPPLY SUPPLY Table 2. Pin Descriptions Name and Function ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle. DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs data during memory array, status register, and identifier code read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. CHIP ENABLE: Activates the device's control logic, input buffers, decoders, and sense amplifiers. CE#-high deselects the device and reduces power consumption to standby levels. RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets internal automation. RP#-high enables normal operation. When driven low, RP# inhibits write operations which provides data protection during power transitions. Exit from deep power-down sets the device to read array mode. RP# at V,, enables setting of the master lock-bit and enables configuration of block lock-bits when the master lock-bit is set. RP#=V,, overrides block lock-bits thereby enabling block erase and byte write operations to locked memory blocks. Block erase, byte write, or lock-bit configuration with VIHcRP#Rev. 1.0 SHARP LHF08CH3 7 2 PRINCIPLES OF OPERATION FFFFF FOOOO EFFFF EOOW DFFFF DO000 CFFFF coooo The LH28F008SCT-L12 SmartVoltage Flash memory includes an on-chip WSM to manage block erase, byte write, and lock-bit configuration functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erasure, byte write, and lock-bit configuration, and minimal processor overhead with RAM-Like interface timings. After initial device power-up or return from deep power-down mode (see Bus Operations), the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby, and output disable operations. Status register and identifier codes can be accessed through the CUI independent of the V,, voltage. High block erasure, voltage on V,, enables successful byte writing, and lock-bit configuration. All functions associated with altering memory contents-block erase, byte write, Lock-bit configuration, status, and identifier codes-are accessed via the CUI and verified through the status register. standard written using Commands are microprocessor write timings. The CUI contents serve as input to the WSM, which controls the block erase, byte write, and lock-bit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and margining of data. Addresses and data are internally latch during write cycles. Writing the appropriate command outputs array data, accesses the identifier codes, or outputs status register data. Interface software that initiates and polls progress of block erase, byte write, and lock-bit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read or write data from any other block. Byte write suspend allows system software to suspend a byte write to read data from any other flash memory array location. BFFFF BOO00 AFFFF AOOW SFFFF 90000 8FFFF 80000 7FFFF 70000 6FFFF 60000 SFFFF 50000 4FFFF 40000 JFFFF 30000 PFFFF 20000 1 FFFF 10000 OFFFF FigUre 3. Memory Map 2: 1 Data Protection Depending on the application, the system designer may choose to make the V,, power supply switchable (available only when memory block erases, byte writes, or lock-bit configurations are required) or hardwired to V,,,,,z13. The device and either design practice accommodates encourages optimization of the processor-memory interface. memory contents cannot be When Vpp~VppLK, altered. The CUI, with two-step block erase, byte write, or lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to V,,. All write functions are disabled when Vcc is below the write lockout voltage VLKO or when RP# is at V,,. The device's block locking capability provides additional protection from inadvertent code or data alteration by gating erase and byte write operations. Rev.1.3 SHARP LHF08CH3 8 3 BUS OPERATION The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. consuming completes. active power until the operatior 3.4 Deep Power-Down mode. RP# at V,, initiates the deep power-down 3.1 Read In read modes, RP#-low deselects the memory places output drivers in a high-impedance state ant turns off all internal circuits. RP# must be held low fo a minimum of 100 ns. Time tPHQv is required afte return from power-down until initial memory acces: outputs are valid. After this wake-up interval, norma operation is restored. The CUI is reset to read array mode and status register is set to 80H. During block erase, ,";~low~ritell o;bo~ck;+; configuration modes, operation. RY/BY# remains low until the rese operation is complete. Memory contents beins altered are no longer valid; the data may be partially erased or written. Time tPHwL is requirod after RPB goes to logic-high (V,,) before another command car be written. As with any automated device, it is important tc assert RP# during system reset. When the systencomes out of reset, it expects to read from the flask memory. Automated flash memories provide status information when accessed during block erase, byte write, or lock-bit configuration modes. If a CPU resei occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. SHARP's flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU. Information can be read from any block, identifier codes, or status register independent of the V,, voltage. RP# can be at either V,, or V,,. The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes, or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep power-down mode, the device automatically resets to read array mode. Four control pins dictate the data flow in and out of the component: CE#, OE#, WE#, and RP#. CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection control, and when active enables the selected memory device. OE# is the data output (DQ,-DQ,) control and when active drives the selected memory data onto the I/O bus. WE# must be at V,, and RP# must be at V,, or V,,. Figure 15 illustrates a read cycle. 3.2 Output Disable JVith OE# at a logic-high level (V,,), the device outputs are disabled. Output pins DC+,-DQ, are olaced in a high-impedance state. 3.3 Standby ZE# at a logic-high level (VI,) places the device in standby mode #which substantially reduces device lower consumption. DQc-DQ, outputs are placed in I high-impedance state independent of OE#. If deselected during block erase, byte write, or lock-bit :onfiguration, the device continues functioning, and Rev. 1.0 LHF08CH3 9 3.5 Read Identifier Codes Operation 3.6 Write The read identifier codes operation outputs the device code, block lock manufacturer code, configuration codes for each block, and the master lock configuration code (see Figure 4). Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algorithms. The block lock and master lock configuration codes identify locked and unlocked blocks and master lock-bit setting. Writing commands to the CUI enable reading 01 device data and identifier codes. They also control inspection and clearing of the status register. When the CUI additionally controls block VPP=VPPHli2/3~ erasure, byte write, and lock-bit configuration. The Block Erase command requires appropriate command data and an address within the block to 5s erased. The Byte Write command requires the command and address of the location to be written. Set Master and Block Lock-Bit commands require ths command and address within the device (Master Lock) or block within the device (Block Lock) to be locked. The Clear Block Lock-Bits command requires the command and address within the device. The CUI does not occupy an addressable memory location. It is written when WE# and CE# are active. The address and data needed to execute a commanc are latched on the rising edge of WE# or CE# (whichever goes high first). Standard microprocessor write timings are used. Figures 16 and 17 illustrate WE# and CE#-controlled write operations. FFFFF FOO04 FOO03 FOO02 Reserved for Future Implementation Block 15 Lock Configuration Code 4 COMMAND DEFINITIONS When the V,, voltage 5 V,,,,, Read operations from the status register, identifier codes, or blocks are enabled. Placing V,,,,,,, on V,, enables successful block erase, byte write and lock-bii configuration operations. 100021 Block 1 Lock Configuration Code 10001 10000 OFFFF Device operations are selected by writing specific commands into the CUI. Table 4 defines these commands. Master Lock Configuration 00002 Code Code 00001~ Block 0 ----------------L-----------------------------------t Lock Configuration Device Code Manufacturer Code Block (I Map Figure 4. Device Identifier Code Memory L RPV I n SHARI= LHF08CH3 10 Mode Read Output Disable Standby Deep Power-Down Read Identifier Codes Write Notes 1,2,3,8 3 3 4 8 3,6,7,8 RP# VT Or HH Table 3. Bus Operations CE# OE# WE# "IL "IL "I, "IL "I, "I, `1, Address X X X X See Figure 4 X VPP X X X X ' X D&.-r DOUT RY/BY# X X X Vn,, "OH "I, Or Or Vr# "I, High Z High Z High Z Note 5 DlN VHH V,, VHH HH X X "IL "I, X X vlH "IL X "IL "IL "I, Or ". Or X `4OTES: I. Refer to DC Characteristics. When VppvPPLK and "PPHl12i3 voltaw for 3. RY/BY# is V,, when the WSM is executing internal block erase, byte write, or lock-bit configuration algorithms. It is VOH during when the WSM is not busy, in block erase suspend mode (with byte write inactive), byte write suspend mode, or deep power-down mode. C. RP# at GNDk0.2" ensures the lowest deep power-down current. i. See Section 4.2 for read identifier code data. i. Command writes involving block erase, write, or lock-bit configuration are reliably executed when Vpp=VppH1/2/3 Block erase, byte write, or lock-bit configuration with V,c<3.OV or VrH |